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TL7231MD september 1999 1 / 37 full layer - iii iso/iec 11172 - 3 audio decoder n single - chip iso/iec 11172 - 3 layer iii audio decoder n supports all mpeg bit rates including free format n supports 32/44.1/48khz sampling frequencies for mpeg bit stream n supports single channel, dual channel, ste reo, and joint stereo n any combination of intensity stereo and ms stereo is supported. n serial bit stream input n 8 - bit host interface port n digital volume control n digital bass/treble control n 6 - band equalizer function n voice record/playback capability n on - chip dac with 1 - bit sigma delta modulation n supports off - chip dac interface n on - chip adc with 12 - bit resolution n power management to reduce power consumption n pll for internal clocks and for output pcm clock generation n single 16.9344mhz external clock input n 3.0 v operation n small footprint 100 - pin thin quad flat package description TL7231MD is a single - chip iso/iec 11172 - 3 layer iii audio decoder, capable of decoding compressed elementary bit streams as specified in iso/iec standard. since it integrated on - chip adc and on - chip dac, it can provide you more small and cheaper solution for mp3 player application. it is designed to be well suited for portable audio appliances. TL7231MD receives the input data bit stream through a serial data interface. the decoded si gnal is 16 - bit serial pcm format that can be sent directly to dac. the generated pcm data can be sent to on - chip dac or off - chip dac according to user preference. the off - chip dac interface is programmable to adapt the pcm output of TL7231MD to the most co mmon dacs used on the market. an 8 - bit host interface port is provided to receive control information from and send status information to host. 8 - bit microcontrollers such as those of intel or motorola can be connected easily. TL7231MD has the capability of compressing voice signals. it can receive voice signals through on - chip adc. the compressed voice signals are transmitted to or received from host through serial data interface. it can also reproduce the voice signals from the compressed voice signals.
TL7231MD 2 /37 samsung electronics co. functional block diagram figure 1. functional block diagram of TL7231MD dma controller serial1 host interface serial0 dac adc reset/ clock unit dsp core unit read data1 write data0 write data1 hd7:0 hale crc program rom constant rom input buffer output buffer working space data read0 data read1 data write0 data write1 dma bus m u x read data0 hrd# hwr# hsel# reset wakeup pwrdn cpuxi cpuxo filter reqstrm clkxrm dxrm timer0 timer1 dacmsck dacbck daclrck dacsdata dacdeem dacmute# aoutl aoutr adcain bus control unit
TL7231MD samsung electronics co. 3 /37 pin description figure 2. 100 - pin thin quad flat package (tqfp) dacvref aoutl nc vss nc vss nc dacvbb vss nc nc vss vddio dacsdata daclrck dacbck dacmsck vss vss vss vss vdd vssio dacmute# dacdeem vdd vss vddio nc nc hwr# hd7 vss vss vss vss vdd nc vssio clkxrm dxrm reqstrm adcvssd adcvddd dacvssa dacvdda dacvhalf aoutr dacvssd dacvddd adcain adcvssa adcvbb adcvdda adcrefn adcrefp pllvdda pllvssa pllvbb filter cpuxo bclk vdd vss vddio vssio reset wakeup vss vss vss vss vdd vss vddio vssio nc nc nc nc vss vss vss vss hd3 hd4 hd5 hd6 hrd# hsel# hale vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 cpuxi vdd vss pwrdn vss hd0 hd1 hd2 TL7231MD top view
TL7231MD 4 /37 samsung electronics co. table 1. pin locations with pin names pin name pin name pin name pin name 1 dacvssa 26 vddio 51 hd3 76 vss 2 dacvdda 27 vssio 52 hd4 77 vss 3 dacvhalf 28 reset 53 hd5 78 vss 4 aoutr 29 wakeup 54 hd6 79 vss 5 dacvssd 30 pwrdn 55 hd7 80 dacmsck 6 dacvddd 31 vss 56 hwr# 81 dacbck 7 adcain 32 vss 57 hrd# 82 daclrck 8 adcvssa 33 vss 58 hsel# 83 dacsdat a 9 adcvbb 34 vss 59 hale 84 dacdeem 10 adcvdda 35 vss 60 vdd 85 dacmute# 11 adcrefn 36 vss 61 reqstrm 86 vssio 12 adcrefp 37 vdd 62 dxrm 87 vddio 13 adcvssd 38 vss 63 clkxrm 88 vss 14 adcvddd 39 vddio 64 vssio 89 vdd 15 pllvdda 40 vssio 65 vddio 90 nc 16 pllvssa 41 nc 66 vss 91 nc 17 pllvbb 42 nc 67 vdd 92 nc 18 filter 43 nc 68 nc 93 vss 19 cpuxo 44 nc 69 nc 94 nc 20 cpuxi 45 vss 70 nc 95 vss 21 vdd 46 vss 71 vdd 96 nc 22 vss 47 vss 72 vss 97 vss 23 bclk 48 hd0 73 vss 98 dacvbb 24 vdd 49 hd 1 74 vss 99 aoutl 25 vss 50 hd2 75 vss 100 dacvref
TL7231MD samsung electronics co. 5 /37 table 2. pin functions with location name pin name pin name pin name pin adcain 7 dacvssa 1 nc 92 vss 34 adcrefn 11 dacvssd 5 nc 94 vss 35 adcrefp 12 dxrm 62 nc 96 vss 36 adcvbb 9 filter 18 pllvbb 17 vss 38 adcvdda 10 hd0 48 pllvdda 15 vss 45 adcvddd 14 hd1 49 pllvssa 16 vss 4 6 adcvssa 8 hd2 50 pwrdn 30 vss 47 adcvssd 13 hd3 51 reqstrm 61 vss 66 aoutl 99 hd4 52 reset 28 vss 72 aoutr 4 hd5 53 vdd 21 vss 73 bclk 23 hd6 54 vdd 24 vss 74 clkxrm 63 hd7 55 vdd 37 vss 75 cpuxi 20 hale 59 vdd 60 vss 76 cpuxo 19 hrd# 57 vdd 67 vss 77 dacbck 8 1 hsel# 58 vdd 71 vss 78 dacdeem 8 4 hwr# 56 vdd 89 vss 79 daclrck 8 2 nc 4 1 vddio 26 vss 88 dacmsck 80 nc 42 vddio 39 vss 93 dacmute# 8 5 nc 4 3 vddio 65 vss 95 dacsdata 8 3 nc 4 4 vddio 87 vss 97 dacvbb 98 nc 68 vss 22 vssio 27 dacvdda 2 nc 69 vss 25 vssio 40 dacvddd 6 nc 70 vss 31 vssio 64 dacvhalf 3 nc 90 vss 32 vssio 86 dacvref 100 nc 91 vss 33 wakeup 29
TL7231MD 6 /37 samsung electronics co. table 3. pin descriptions signal name type description internal pll interface cpuxi i cpu clock in. 16.9344mhz crystal clock input. cpuxo o cpu clock out. 16.9344mhz crystal clock output. filter o charge pump out. external capacitor should be connected between this pin and analog gro und. clock signal bclk o processor clock output. reset & power down control reset i chip reset. reset input to the chip. internal pull down. wakeup i wake up. when high, chip is waked up from sleep state. this pin should be remained active at least 1 clock cycle and inactive before the host issues next sleep command. internal pull down. pwrdn i power down. this pin controls pwrdown state. when high, chip goes to very low power consumption state. after deactivation, wakeup pin should be remained low at least 150 m s. internal pull down. (restriction: this pin should be active only in sleep state. otherwise, chip reset should be activated.) mcu serial interface clkxrm i serial clock. mcu serial interface clock . dxrm i/o serial data. when mcu transmits data, this data pin is sampled at negative edge of clkxrm. when mcu receives data, data is valid from negative edge of clkxrm to next negative edge of clkxrm. dxrm should be sampled at positive edge of clkxrm. after reset, TL7231MD is set to transmit the most signifi cant bit first. reqstrm o request bit stream data. mcu must check this pin to determine to continue receiving or transmitting. mcu should transmit or receive data during this signal active. mcu hip(host interface port) interface hsel# i hip enable. when low, hip is selected. hale i hip address latch enable. when high, hd[7:0] should have hip address, which is sampled at negative edge of this signal. hrd# i hip read enable. when low, data is loaded to hd[7:0], which should be sampled at positive edge of this signal. hwr# i hip write enable. data at hd[7:0] is sampled at positive edge of this signal. hd[7:0] i/o hip address/data bus. multiplexed address lines and data lines. internal adc interface adcain i adc analog input. analog input spans between adcrefp and adcrefn. adcrefp i adc internal reference top bias . connect this pin to voltage between adcvdda and 2.0v. adcrefn i adc internal reference bottom bias. connect this pin to ground.
TL7231MD samsung electronics co. 7 /37 adcvdda pwr adc supply voltage for analog circuit. connect t his pin to the +3.0v supply voltage. adcvssa gnd adc ground for analog circuit. connect this pin to ground. adcvddd pwr adc supply voltage for digital circuit. connect this pin to the +3.0v supply voltage. adcvssd gnd adc ground for digital circuit. con nect this pin to ground. adcvbb gnd adc analog/digital bulk bias. connect this pin to ground. external dac interface dacmsck o dac master clock. 384 fs clock. dacbck o dac bit clock. 32 fs clock . daclrck o dac sample rate clock. fs clock. dacsdata o dac serial data. serial data . dacdeem o dac deemphasis. when deemphasis is on, this signal is high. it can be set/clear through hip commands. dacmute# o dac mute. analog output mute. when external dac is set to mute on, this signal is low. it can be set /clear through hip commands. internal dac interface aoutl o analog output for left - channel. aoutr o analog output for right - channel. dacvhalf i/o dac reference voltage output for bypass. dacvref i/o dac reference voltage output for bypass. dacvdda p wr dac supply voltage for analog circuit. connect this pin to the +3.0v supply voltage. dacvssa gnd dac ground for analog circuit. connect this pin to ground. dacvddd pwr dac supply voltage for digital circuit. connect this pin to the +3.0v supply voltag e. dacvssd gnd dac ground for digital circuit. connect this pin to ground. dacvbb gnd dac pad bulk bias. connect this pin to ground. power/ground pins vdd pwr supply voltage. connect this pin to the +3.0v supply voltage. vss gnd circuit ground. connec t this pin to ground. vddio pwr supply voltage for i/o buffers. connect this pin to the +3.0v supply voltage. vssio gnd circuit ground for i/o buffers. connect this pin to ground.
TL7231MD 8 /37 samsung electronics co. functional description reset/clock unit TL7231MD is driven by a single clock at the frequency of 16.9344mhz. the clock is derived from an external source or from an industry standard crystal oscillator, generating input frequency of 16.9344mhz. the clock generation unit has a pll, and all the internal clock signals including internal dac/adc clocks are generated with the input clock. when TL7231MD is in power - on - reset, reset signal should be active at least 150 m s till the internal pll is stabilized. to reset TL7231MD during normal operation, reset signal should be active at least 16 cycles. figure 3. clock circuit dsp core logic the core logic of TL7231MD is a 32 - bit floating - point dsp processor. the indep endent multiplier and accumulator of TL7231MD can achieve high performance . internal registers are 40 - bit registers that store values with a 32 - bit mantissa and an 8 - bit exponent. these registers can serve as both the source and destination for any arithme tic operation. since all the data input/output transactions are managed by dma, there is no computational overhead due to data transactions. serial interface the serial interface of TL7231MD is used to receive mpeg bit stream data or transmit/receive vo ice data. it is configured to transfer 8 bits of data per word. it can be configured to be lsb - first or msb first transfer mode. lsb - first means that the data bits are transmitted and received least - significant bit (lsb) first. msb - first means that the dat a bits are transmitted and received most - significant bit (msb) first. the clock for the serial interface should be generated externally. the related signals are clkxrm, dxrm, and reqstrm. reqstrm is used for synchronization between microcontroller and tl 7231md, and data is transferred during reqstrm active. cpuxi 16.9344mhz cpuxo filter TL7231MD 1m 30p 30p 820p
TL7231MD samsung electronics co. 9 /37 when microcontroller tries to send data to TL7231MD, it should check whether reqstrm is active or not. if the signal is active, microcontroller sets its serial interface to transmit mode and send seri al clock and serial data. after transmitting each byte, microcontroller should check reqstrm to decide whether next byte is to be transmitted or not. when microcontroller tries to receive data from TL7231MD, it should check whether reqstrm is active or no t. if the signal is active, microcontroller sets its serial interface to receive mode and send serial clock and receive serial data from TL7231MD. after receiving each byte, microcontroller should check reqstrm to decide whether TL7231MD will transmit next byte or not. host interface port (hip) host interface port is used to send commands to and receive status information from TL7231MD. hip of TL7231MD is a parallel i/o port that makes a connection to a host processor easily . through the hip, tl 7231 md ca n be used as a memory - mapped peripheral to a host processor . the hip can be thought of as an area of dual - port memory that allow s communication between the computational core of the TL7231MD and host. the hip is completely asynchronous. the host processor can write data into the hip while the TL7231MD is operating at full speed. hip transfers are managed using interrupt scheme. hip contains 21 registers. four of them are data - in registers (hdi0/hdi1/hdi2/hdi3) and one of them is a status register (hsr4). the remaining 16 registers are data - out registers (hdo0/ ? /hdo15). data written into hdis by host are read by TL7231MD. through these registers host can give necessary commands to TL7231MD. a command is written into a hdi0, and the required parameters of th e command are written into the hdi1/hdi2/hdi3. the status register (hsr4) keeps the information whether data written into the data - in registers are read by TL7231MD. the status register is managed automatically by TL7231MD and can be read by host. TL7231MD starts hip command processing when hdi0 register is written. so if any command requires parameters, user should write parameters first, and then write command. serial id number can be used to check whether given command has been accepted or not. TL7231MD can receive the serial id value through hdo0 when TL7231MD has accepted the given command. thus when commands are given to TL7231MD with different serial id numbers, it can be examined which command is being processed. serial id number itself hasn?t any s pecial meaning. if this feature is not needed, it is not required to send id values with commands. then the value of hdo0 is undetermined. there is an exception for the id number convention. if you use hip command 0dh(revision code), TL7231MD returns the t l7231md revision number, not the id number. hdos are written by TL7231MD and can be read by host. all hip registers should be memory - mapped into the memory space of the host processor . the address space of those registers is shown in table 4. the usable commands are listed in table 6. the contents reported by hdos are shown from figure 4 to figure 16. table 4. address of host interface port registers
TL7231MD 10 /37 samsung electronics co. address registers description 0h hdi0 command 1h hdi1 serial id number 2h ~ 3h hdi2/hdi3 parameters if needed 4h hsr4 status register (fig. 4) 10h hdo0 command serial id number (fig. 5) 11h hdo1 decoder state (fig. 6) 12h hdo2 io status (fig.7) 13h hdo3 io status (fig. 8) 14h hdo4 volume (fig. 9) 15h hdo5 serial interface mode (fig. 10) 16h ~ 1fh hdo6 ~ hdo15 the information provided by these registers depends on the mode setting of TL7231MD. (refer to table 5) the information provided by hdo6 to hdo15 depends on the mode setting of TL7231MD. refer to table 5. the mode can be set by using hip command 19h(report format). for this command, refer to table 6. table 5. the contents of hdo6 ~ hdo15 according to mode setting address registers description 16h hdo6 mode0: 00h mode1: tone control status. when tone control is enabled, 1 is reported. otherwise, 0 is reported. mode2: mp3 frame count (fig. 11) mode3: voice data code count (fig. 11) mode4: equalizer control status. when equalizer control is enabled, 1 is reported. otherwise, 0 is reported. 17h hdo7 mode0: 00h mode1: tone control - presca ling information mode2: mp3 frame count (fig. 11) mode3: voice data code count (fig. 11) mode4: eq control ? prescaling information 18h hdo8 mode0: 00h mode1: tone control ? bass cutoff frequency mode2: mp3 frame count (fig. 11) mode3: voice data code cou nt (fig. 11) mode4: eq control ? band1 gain 19h hdo9 mode0: 00h mode1: tone control ? bass gain mode2: mp3 frame count (fig. 11) mode3: voice data code count (fig. 11) mode4: eq control ? band2 gain 1ah hdo10 mode0: 00h
TL7231MD samsung electronics co. 11 /37 mode1: tone control ? treble cutoff frequency mode2: the most recently synchronized frame header of mp3 bit stream. (fig. 12) mode3: 00h mode4: eq control ? band3 gain 1bh hdo11 mode0: 00h mode1: tone control ? treble gain mode2: the most recently synchronized frame header of mp3 bit strea m. (fig. 13) mode3: 00h mode4: eq control ? band4 gain 1ch hdo12 mode0: 00h mode1: 00h mode2: the most recently synchronized frame header of mp3 bit stream. (fig. 14) mode3: 00h mode4: eq control ? band5 gain 1dh hdo13 mode0: 00h mode1: 00h mode2: bass b oost information (fig. 15) mode3: 00h mode4: eq control ? band6 gain 1eh hdo14 mode0: 00h mode1: 00h mode2: dac output valid (fig. 16) mode3: 00h mode4: 00h 1fh hdo15 mode0: 00h mode1: 00h mode2: crc error count mode3: 00h mode4: 00h
TL7231MD 12 /37 samsung electronics co. table 6. host int erface port commands comm and parame ter meaning description 00h none stop stop execution and go into wait state. 01h none mp3 decoding execute mp3 decoding. 04h none voice encoding execute voice encoding (16kbps). 05h none voice decoding execute voice d ecoding (16kbps). 06h none voice encoding execute voice encoding (24kbps). 07h none voice decoding execute voice decoding (24kbps). 08h none voice encoding execute voice encoding (32kbps). 09h none voice decoding execute voice decoding (32kbps). 0dh n one revision code report the TL7231MD revision number in hdo0. 0fh none sleep go into sleep state. this command should be used in wait state. if this command is used during algorithm execution, TL7231MD becomes unstable. 10h none mute on when using inter nal dac, the output voltage level of aoutl/aoutr is gnd. when using external dac, dacmute# becomes active. after reset, TL7231MD is set to be mute on. 11h none mute off mute is disabled. 12h none internal adc use internal adc. external adc interfaces are disabled. after reset, it is the default value. 14h none internal dac use internal dac. after reset, it is set to use internal dac. 15h none external dac use external dac. internal dac is disabled. the waveform of i/o pin related to external dac is cont rolled according to external dac format or external dac format 2. 16h 1byte external dac format set the waveform of i/o pin related to external dac. the parameter value of external dac format command should be as follows: {0, 0, 0, 0, 0, i 2 s, pl, pb}. for the meaning of i 2 s, pl, and pb, refer to figure 8. 17h none msb first serial interface msb - first mode. this is the default mode after reset. 18h none lsb first serial interface lsb - first mode the reported contents of hdo6 to hdo 15 are changed according to parameter of this command. parameter reporting contents 0 all 00h 1 tone control information 2 mp3 decoding information 3 voice encoding/decoding information 4 equalizer control informa tion 19h 1byte report format
TL7231MD samsung electronics co. 13 /37 20h 1byte bass boost control (mp3 only) control bass boost. the upper nibble of the parameter controls the cutoff frequency of bass boost, and the lower nibble controls the level of bass boost. the value of upper nibble should be in the rang e of 0 to 6. the cutoff frequency is 25 upper nibble + 50 (hz). if the values of the lower nibble is in the range of 0 to 12, the low frequency band below the cutoff frequency is boosted by 0db ~ 18db (1.5db step). the other values mean no boost. fo r example, if the parameter value is 42h, then the cutoff frequency will be 25 4+50=150hz, and the frequency band below 150hz will be boosted by 3db compared to the upper frequency band. in case of using bass boost, volume is reduced by 1.5 n db where n means the parameter value. the reset value is ffh(disabled). 21h 1byte volume control control volume. the parameter should have the value of range from 0 to 255. if the value is n , the volume is attenuated by n /2 db compared to maximum volume. the reset v alue is 0. 22h 1byte prescale control control the prescaling. the parameter is a signed value and can be - 128 to 127. the prescaling is done by 0.5 n db according to parameter value n . that is, 0h ~ 7fh means 0db ~ 63.5db scaling, 80h ~ ffh means ? 64db ~ - 0.5db scaling. the reset value is 0db. 23h 1byte tone control ? bass gain (mp3 only) control the bass gain. the parameter is a signed value and can be - 128 to 127. the gain can be 0.5 n db according to parameter value n . the reset value is 0. 24h 1byte tone control ? treble gain (mp3 only) control the treble gain. the parameter is a signed value and can be - 128 to 127. the gain can be 0.5 n db according to parameter value n . the reset value is 0. 25h 1byte tone control ? bass cutoff (mp3 on ly) control the bass cutoff frequency. the parameter can have the value of 0 to 255. the cutoff frequency can be 20 + 5 n hz according to parameter value n . the reset value is 0. 26h 1byte tone control ? treble cutoff (mp3 only) control the treble cuto ff frequency. the parameter can have the value of 0 to 255. the cutoff frequency can be 5000 + 20 n hz according to parameter value n . the reset value is 0. 27h none tone control ? enable (mp3 only) enable the tone control function. tone control function is disabled when reset. 28h none tone control ? disable (mp3 only) disable the tone control function. tone control function is disabled when reset. 30h none mp3 crc bypass (mp3 only) during mp3 decoding, even if the input bit stream contai ns the crc field, TL7231MD doesn?t check the crc error. after reset, TL7231MD is set to check crc error.
TL7231MD 14 /37 samsung electronics co. 31h none mp3 crc check during mp3 decoding, if the input bit stream contains the crc field, check the crc error. if an error occurs , TL7231MD outputs 0 during the period of corresponding mp3 frame. the reset value is mp3 crc check. 40h 1byte eq control ? band1 gain (mp3 only) control the gain of band1(<30hz) of 6 - band equalizer. the parameter is a signed value and can be - 128 to 127. the gain can be 0.5 n db according to parameter value n . the reset value is 0db. 41h 1byte eq control ? band2 gain (mp3 only) control the gain of band2(30hz~125hz) of 6 - band equalizer. the parameter is a signed value and can be - 128 to 127. the gain can be 0.5 n db according to parameter value n . the reset value is 0db. 42h 1byte eq control ? band3 gain (mp3 only) control the gain of band3(125hz~500hz) of 6 - band equalizer. the parameter is a signed value and can be - 128 to 127. the gain can be 0.5 n db accordin g to parameter value n . the reset value is 0db. 43h 1byte eq control ? band4 gain (mp3 only) control the gain of band4(500hz~2khz) of 6 - band equalizer. the parameter is a signed value and can be - 128 to 127. the gain can be 0.5 n db according to param eter value n . the reset value is 0db. 44h 1byte eq control ? band5 gain (mp3 only) control the gain of band5(2khz~8khz) of 6 - band equalizer. the parameter is a signed value and can be - 128 to 127. the gain can be 0.5 n db according to parameter value n . the reset value is 0db. 45h 1byte eq control ? band6 gain (mp3 only) control the gain of band6(>8khz) of 6 - band equalizer. the parameter is a signed value and can be - 128 to 127. the gain can be 0.5 n db according to parameter value n . the reset va lue is 0db. 46h none eq control ? enable (mp3 only) enable the equalizer function. the equalizer function is disabled after reset. 47h none eq control ? disable (mp3 only) disable the equalizer function. the equalizer function is disabled a fter reset. 8xh none external dac format2 same as external dac format command. parameter values are located at lower nibble of the command. the command should be the form of {1, 0, 0, 0, 0, i 2 s, pl, pb}.
TL7231MD samsung electronics co. 15 /37 bass boost control command(20h) is another form of tone control command(23h ~28h). it is implemented by using the same filter as tone control command. thus, if bass boost control command is received with valid parameter value, gains and cutoffs are changed as follows; l bass gain and cutoff frequency of tone control are changed according to the parameter value. l treble gain is changed to 0. l prescaling is set to ? 12db to remove clipping noise. l tone control is enabled. if bass boost command is received with invalid parameter value, the gains and cutoff fre quencies are not changed, and tone control is disabled. if a command related to tone control is received, only the related gain or cutoff frequency is changed, and the command has no effect on the tone control enable/disable and prescaling, and the informa tion of bass boost which is reported through hdo13 is not changed. for the tone control enable command(27h), it just enables the tone control function, and has no effect on the gains and cutoff frequencies. tone control disable command(28h) disable tone co ntrol function, and change the bass boost status which is reported through hdo13 to ffh(disable). prescaling has effect when tone control or equalizer is enabled or bass boost command is received. equalizer consists of 6 bands, and band1 and band6 are sh elving type, band2 to band5 are peaking type. since each band has relatively small q value, correction matrix is automatically used to complement this small q value whenever attenuation value is set by using eq gain control commands(40h ~ 45h). it is not r ecommended that gain difference of neighbor bands exceeds 10db.
TL7231MD 16 /37 samsung electronics co. 7 6 5 4 3 2 1 0 reserved s3 s2 s1 s0 bit number bit mnemonic function 3 s3 when set, it means that host wrote parameter to hdi3 register, but it isn ? t read by TL7231MD. 2 s2 when set, it means that host wrote parameter to hdi2 register, but it isn ? t read by TL7231MD. 1 s1 when set, it means that host wrote command id to hdi1 register, but it isn ? t read by TL7231MD. 0 s0 when set, it means that host wrote command to hdi0 register, but it isn ? t read by TL7231MD. figure 4. hdi status reported through hsr4 7 6 5 4 3 2 1 0 id bit number bit mnemonic function 7:0 id serial id number figure 5. command id reported through hdo0
TL7231MD samsung electronics co. 17 /37 7 6 5 4 3 2 1 0 state bit number bit mnemonic function 7:0 state TL7231MD status report 00h: wait state 01h: mp3 decoding 04h: voice encoding (16kbps) 05h: voice decoding (16kbps) 06h: voice encoding (24kbps) 07h: voice decoding (24kbps) 08h: voice encoding (32kbps) 09h: voice decoding (32kbps) figure 6. TL7231MD status reported through hdo1
TL7231MD 18 /37 samsung electronics co. 7 6 5 4 3 2 1 0 reserved de mu# sf bit number bit mnemonic function 3 de deemphasis enable: when set, deemphasis is enabled. reset value is 0. 2 mu# mute enable: when cleared, mute is on. reset value is 0. 1:0 fs sampling frequency: during mp3/voice decoding, it shows the sampling frequency of bit stream. daclrck is set as follows: 00: 44.1khz 01: 48khz 10: 32khz 11: not used during voice encoding, it shows the sampling frequency of bit stream. adcaden# is set as follows: 00: not used 01: not used 10: not used 11: 8khz reset value is 00. figure 7. i/o status r eported through hdo2
TL7231MD samsung electronics co. 19 /37 7 6 5 4 3 2 1 0 reserved i2s pl pb edac eadc bit number bit mnemonic function 4 i2s i 2 s format enable: when set, i 2 s format (1 bit delay), when cleared normal pcm format. reset value is 0. 3 pl pol arity of daclrck: when cleared, left channel data is sent through dacsdata during lrck=0. when set, right channel data is sent through dacsdata during lrck=0. reset value is 0. (refer figure17.) 4 pb polarity of dacbck: when cleared, dacsdata has valid data between falling edges of dacbck. when set, dacsdata has valid data between rising edges of dacbck. (refer figure17.) reset value is 0. 1 edac external dac enable: when set, external dac is used. reset value is 0. 0 eadc external adc enable: when set, external adc is used. reset value is 0. figure 8. i/o status reported through hdo3 7 6 5 4 3 2 1 0 volume bit number bit mnemonic function 7:0 volume the value can be 0 to 200. figure 9. volume reported throug h hdo4
TL7231MD 20 /37 samsung electronics co. 7 6 5 4 3 2 1 0 mode bit number bit mnemonic function 0 mode serial interface mode. when set, lsb - first mode. when cleared, msb - first mode. the reset value is 0. figure 10. serial interface mode reported through hdo 5 7 6 5 4 3 2 1 0 hdo9 hdo8 hdo7 hdo6 bit number bit mnemonic function hdo9 7:0 hdo8 7:0 hdo7 7:0 hdo6 7:0 these registers show 32 - bit unsigned integer value. hdo9 is the most - significant byte. when mode is 2, it represents the successfully decoded frame counter during mp3 decoding. when mode is 3, it represents the encoded/decoded code count during voice encoding/decoding. figure 11. count value reported through hdo6 ~ hdo9
TL7231MD samsung electronics co. 21 /37 7 6 5 4 3 2 1 0 reser ved id layer pt bit number bit mnemonic function 3 id 0: reserved 1: iso/iec standard 11172 - 3 audio (mp3) 2:1 layer 00: reserved 01: layer3 10: layer2 11: layer1 TL7231MD decodes only layer3 bit stream. 0 pt protection bit: 0: crc protect ion 1: no crc protection figure 12. frame header reported through hdo10 when mode is 2.
TL7231MD 22 /37 samsung electronics co. 7 6 5 4 3 2 1 0 bri sf pd pr bit number bit mnemonic function 7:4 bri bit rate index: 0000: free 0001: 32kbps 0010: 4 0kbps 0011: 48kbps 0100: 56kbps 0101: 64kbps 0110: 80kbps 0111: 96kbps 1000: 112kbps 1001: 128kbps 1010: 160kbps 1011: 192kbps 1100: 224kbps 1101: 256kbps 1110: 320kbps 1111: forbidden 3:2 sf sampling frequency: 00: 44.1khz 01: 48khz 10: 32khz 11: reser ved 1 pd padding bit 0: no padding bit 1: one padding bit 0 pr private bit bit for private use. figure 13. frame header reported through hdo11 when mode is 2.
TL7231MD samsung electronics co. 23 /37 7 6 5 4 3 2 1 0 mode me cr oc em bit number bit mnemoni c function 7:6 mode audio channel mode: 00: stereo 01: joint stereo (intensity stereo and/or ms stereo) 10: dual channel 11: single channel 5:4 me joint stereo coding method: 00: neither intensity stereo nor ms stereo 01: only intensity stereo 10: on ly ms stereo 11: both intensity stereo and ms stereo 3 cr copyright: 0: no copyright 1: copyright protected 2 oc original/copy: 0: copy 1: original 1:0 em type of deemphasis: 00: none 01: 50/15 microseconds 10: reserved 11: ccitt j.17 dacdeem of t l7231md becomes active if deemphasis is needed without relation to deemphasis type. figure 14. frame header reported through hdo12 when mode is 2.
TL7231MD 24 /37 samsung electronics co. 7 6 5 4 3 2 1 0 cf bb bit number bit mnemonic function 7:4 cf cutoff frequency: the value can be in the range of 0 to 6. 3:0 bb base boost value figure 15. bass boost information reported through hdo13 when mode is 2. 7 6 5 4 3 2 1 0 valid bit number bit mnemonic function 0 valid dac outp ut valid: when set, output of internal dac is valid. reset value is 0. figure 16. dac output status reported through hdo14
TL7231MD samsung electronics co. 25 /37 dac dac of TL7231MD employs the 1 - bit 4 th - order sigma - delta architecture with 16 - bit resolution, over - sampling of 64x. ana log post - filter with low clock sensitivity and linear phase can filter out the shaping - noise and output analog voltage with high resolution. the characteristic of internal dac is shown table 7. table 7 . characteristics of internal dac parameter min typ ma x units resolution 16 bits snr 79.7 db thd 84.9 db sndr 78.5 db reference voltage output (dacvref) 0.5 dacvdda v frequency response 0.1 0.5 db analog output voltage range 0.5 dacvdda vpp load impedance 10k w digital filter p ass band ripple 0.0072 db stop and attenuation 62.7 db pass band 0.45 fs (dacvddd/dacvdda=3.0v, temp=25 c, fs=44.1khz, signal freq.=20~20khz, c load of aoutl/aoutr = 10pf) with TL7231MD, user can configure whether the internal dac is used or no t. the configuration of dac can be achieved through hip commands shown in table 5. when using internal dac, the following circuit in figure 17 is recommended.
TL7231MD 26 /37 samsung electronics co. figure 17. reference circuit when using internal dac dacvdda dacvssa dacvbb dacvddd dacvssd 3.0v 10 u 0.1 u 10 u 0.1 u 3.0v TL7231MD aoutr aoutl dacvhalf dacvref low pass filter (optional) low pass filter (optional) rout lout 10 u 10 u 0.1 u 0.1 u 1 u 1 u 100k 100k
TL7231MD samsung electronics co. 27 /37 external dac inter faces TL7231MD supports eight external interface formats. three of them, for example, are shown in figure 18. the interface can be configured through hip commands. the frequency of dacbclk is 32 times of that of daclrck. when voice decoding, only 32khz of daclrck is used. figure 18. examples of external dac interfaces msb-2 msb-1 msb lsb+2 lsb+1 lsb msb-2 msb-1 msb lsb+2 lsb+1 lsb daclrck dacbck dacsdata right-justified mode (edac: 1, pb: 0, pl: 0, i 2 s: 0) msb-1 msb lsb+2 lsb+1 lsb msb-1 msb lsb+2 lsb+1 lsb daclrck dacbck dacsdata i 2 s-justified mode (edac: 1, pb: 0, pl: 0, i 2 s: 1) msb-2 msb-1 msb lsb+2 lsb+1 lsb msb-2 msb-1 msb lsb+2 lsb+1 lsb daclrck dacbck dacsdata right-justified mode (edac: 1, pb: 1, pl: 1, i 2 s: 0) left channel right channel left channel right channel left channel right channel
TL7231MD 28 /37 samsung electronics co. adc the internal adc of TL7231MD is 12 - bit resolution adc. it is recycling type adc with sample - and - hold function. the analog input adcain should be single - ended type with the range fro m adcrefp to adcrefn. this adcain voltage follows reference voltage range fundamentally. so, if user wants to alter the input range, the voltage value of adcrefp should be changed. but adcrefp should be greater than 2.0v. the characteristic of internal adc is shown table 8. table 8 . characteristics of internal adc parameter min typ max units thd 74.3 db snr 64.9 db sndr 64.4 db (adcvddd/adcvdda=3.0v, adcain=8khz) figure 19. reference circuit when using internal adc with TL7231MD, the follow ing circuit in figure 19 is recommended to use internal adc. adcvdda adcvssa adcvbb adcvddd adcvssd adcain adcrefp adcrefn 3.0v vref 10 u 0.1 u 10 u 0.1 u 3.0v adcrefp/2 10 u 0.1 u TL7231MD adcrefn adcrefp
TL7231MD samsung electronics co. 29 /37 voice record/playback function TL7231MD records voice data from adc in 8khz sampling rate. there are three compression modes according to bit rates of compressed data: high quality (32kbps), me dium quality (24kbps) and low quality (16kbps). in high quality mode, relatively large bits are allocated for compressed data to achieve high quality of the sound. in low quality mode, smaller bits are allocated to record much more samples in the same size of storage media. medium quality mode gives tradeoff between high and low quality modes. compressed codes are byte - aligned and transmitted to host mcu through the serial port. in playback the codes are uncompressed to pcm samples, with the compression mo de in recording, and then oversampled to 32 khz and output to dac. compressed codes are transmitted from host mcu through the serial interface. table 9 is the summary of the relation between compression modes and code size. table 9. summary of three voic e compression modes compression modes code length (bit) recording time for 32mb storage med ia high quality (32kbps) 4 140 min. medium quality (24kbps) 3 186 min. low quality (16kbps) 2 280 min.
TL7231MD 30 /37 samsung electronics co. lower power operation TL7231MD has low - power feature t hat makes the processor get into very low - power dormant states through hardware or software control. the power saving scheme is explained with the state diagram of TL7231MD shown in figure 20. run in this state, TL7231MD decodes mp3 or compressed voice bi t stream, or encodes voice signal. also in this state it can process other hip commands such as 20h and 21h. hip command 01h, 04h through 09h, and 0fh should not be used in this state. TL7231MD consumes normal power at this state, it processes all internal functions and drives external pads. it can transit to wait state with hip command 00h. when there is no job left or it waits available data, power consumption is reduced as that of wait state. wait when reset signal becomes active, TL7231MD goes into wa it state. there it can transit to run, or sleep state. when TL7231MD is in this state, it is ready to receive any hip commands from host. it can go into run state when it receives hip commands such as 01h, 04h though 09h. also it can process other hip comm ands such as volume control (21h) etc. in this state. TL7231MD goes into this state through hip command 00h from run state. when TL7231MD is in this state, only peripheral interface block consumes power. that is, internally generated peripheral clock is ac tive but clock for the dsp core logic is not. when it receives hip command 0fh, it goes into sleep state in which more power is saved. sleep in sleep state, only internal analog blocks such as pll, adc and dac of TL7231MD consume power. in this state, int ernal adc and dac are disabled. but pll consumes normal operation power. in this state, TL7231MD can transit to pwrdown state when external pwrdn pin becomes active. active wakeup signal changes its state from sleep to wait. pwrdown when TL7231MD is in s leep state and pwrdn signal becomes active, it transits to pwrdown. to make TL7231MD stay in this state, the external pwrdn signal keep its active state. when the pwrdn signal becomes inactive, TL7231MD exits from this pwrdown state, and then goes into sle ep state. when it changes its state from pwrdown to sleep, this state should not be changed during minimum 150 m s until internal pll is stabilized. TL7231MD consumes the minimum power at this state because all internal logic blocks and analog blocks are power - downed.
TL7231MD samsung electronics co. 31 /37 figure 20. decoder states and power management wait run sleep pwr- down pwrdn pin hip command (00h) hip command hip command (0fh) wakeup pin pwrdn pin reset
TL7231MD 32 /37 samsung electronics co. electrical specifications absolute maximum ratings (see notes) ? symbol parameter rating unit v dd dc supply voltage - 0.3 to 3.8 v v in dc input voltage - 0.3 to 5.5 v i in dc input current 10 ma t stg storage temperature - 40 to 125 c ? stresses beyond those listed under ? ab solute maximum rating s? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? dc electrical characteristics ? is not implied. exposure to absolute - maximum - ra ted conditions for extended periods may affect device reliability. note 1: all voltage values are with respect to v ss . note 2: this value was obtained under specially produced worst - case test conditions for the TL7231MD , which are not sustained during nor mal device operation. dc electrical characteristics (note3) ? symbol parameter min typ max unit v dd supply voltage 2.7 3.0 3.3 v v ss supply voltage 0 v v ih high level input voltage 1.8 v dd +0.3 v v il low level input voltage - 0.3 0.6 v v oh high le vel output voltage 2 v v ol low level output voltage 0.4 v i ih high level input leakage current without internal pull - up - 10 +10 m a i il low level input leakage current without internal pull - up - 10 +10 m a i rn supply current in run state 61 ma i w t supply current in wait state 26 ma i sl supply current in sleep 12 ma i pd supply current in pwrdown state 250 m a c in input capacitance 4 pf c out output capacitance 4 pf t a air temperature - 40 85 c v cpuxi high level input voltage for cpuxi 2.5 v dd +0.3 v ? for TL7231MD , all typical values are at v dd = 3.0 v, t a (air temperature) = 25 c . n ote 3: all vol tage values are with respect to v ss . all input and output voltage levels are ttl - compatible. clkin can be driven by cmos clock. notice: this document contains information on products in the sampling and initial production phases of development. the speci fications are subject to change without notice.
TL7231MD samsung electronics co. 33 /37 ac electrical characteristics ac test condition parameter value temperature 85 c supply voltage 3.0v input rise and fall times 2ns output load 10pf serial port the following table defines the timin g parameters for the serial port pins. the numbers shown in figure 21 correspond to each number in the first column of the table. no. symbol description min max unit 1 t cc cycle time of clkxrm 144.7 ns 2 t d delay time, clkxrm to dxrm valid 42.2 78.4 ns 3 t su setup time, dxrm before clkxrm low 1.9 ns 4 t h hold time, dxrm from clkxrm low 1.2 ns 5 t req request check time, falling edge of clkxrm to falling edge of reqstrm 295.2 331.3 ns figure 21. timing for serial port in case of lsb - first mode dxrm (transmit) dxrm (receive) clkxrm 3 4 2 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 reqstrm 5 1
TL7231MD 34 /37 samsung electronics co. host interface port the following table defines the timing parameters for the host interface port i/o pins. the numbers shown in figure 22 correspond to each number in the first column of the table. no. symbol description min max unit 6 t haw hale pulse width 2.0 ns 7 t hdsu setup time, hd address setup before hale low 2.0 ns 8 t hdh hold time, hd address hold after hale low 0.8 ns 9 t has start of write or read after hale low 0.0 ns 10 t hdsu setup time, hd data setup before end of write 0.7 ns 11 t hdh hold time, hd data hold after end of write 2.2 ns 12 t hrw read or write pulse width 36.2 ns 13 t hde hd data enabled after start of read 7.8 ns 14 t hdd hd data valid after start of read 7.9 ns 15 t hrdh hd data hold after end of read 3.7 7.8 ns 16 t hrdd hd data disabled after end of read 4.2 7.9 ns
TL7231MD samsung electronics co. 35 /37 figure 22. timing for host interface port pins hale hsel# hwr# hd[7:0] hale hsel# hrd# hd[7:0] 10 6 12 9 7 8 14 13 16 15 host write cycle host read cycle data address address data 11 5 9 7 8 12
TL7231MD 36 /37 samsung electronics co. package dimension
TL7231MD samsung electronics co. 37 /37 the reproduction of this datasheet is not allowed without approval of sec. all in formation and data contained in this datasheet are subject to change without notice. this publication supersedes and replaces all information previously supplied. sec has no responsibility to the consequence of using the patents described in this document. ? 1999 samsung electronics co., ? all rights reserved

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